The invention relates to a control signal generator for processing a video signal. Such a control signal generator can be used, for example for coding video pictures. In this case it forms part of a coder as described, for example in DE36 13 343 and corresponding U.S. Pat. No. 4,825,285.
A basic signal and television test signal generator is known from EP 00 34 956 and corresponding U.S. Pat. No. 4,468,337 in which the amplitudes of the basic and test signals are stored in an addressable memory. The memory is directly addressed by a first counter and indirectly by a second counter via a further memory in which addresses for the first memory are stored. The two counters are clocked with clock signals of different frequencies and essentially correspond to a line and pixel counter. The known arrangement can be synchronised by means of a synchronising signal with other arrangements of a similar construction.
It is an object of the invention to provide a control signal generator whose output signal can synchronise a video signal using field synchronisation pulses, while the phase of the field synchronising pulses relative to the associated video signal is arbitrary.